Electro-optical display device and display method thereof

ABSTRACT

A method of reducing power consumption of an electro-optical display device which can display a still image with the use of analog signals. A circuit in which a small amount of leakage current flows between a source and a drain of a selection transistor when the selection transistor is off; the source of the selection transistor is connected to a gate of an N-channel driving transistor, a gate of a P-channel driving transistor, and one electrode of a capacitor; and a source of each of the N-channel driving transistor and the P-channel driving transistor is connected to one electrode of a display element is provided in each pixel. The longest time of one frame is set to 100 seconds or longer with the use of such a circuit, whereby power consumption at the time of rewriting is reduced.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a display device utilizing electricalresponse characteristics of a material. The present invention relatesto, for example, a liquid crystal display device or the like.

2. Description of the Related Art

In an active matrix liquid crystal display device which is a typicalelectro-optical display device, a circuit including a transistorWTr_((n,m)), a capacitor (also referred to as a storage capacitor)C_((n,m)), and a liquid crystal display element LC_((n,m)) asillustrated in FIG. 2A is provided in each pixel.

FIG. 2B is an equivalent diagram illustrating a state where the circuitholds charges. The capacitor C_((n,m)) has capacitance C₁ and resistanceR₁, the liquid crystal display element LC_((n,m)) has capacitance C₂ andresistance R₂, and the transistor WTr_((n,m)) has resistance R₃. Thecapacitance C₁ of the capacitor C_((n,m)) is usually several times ormore as high as the capacitance C₂ of the liquid crystal display elementLC_((n,m)).

Ideally, it is desirable that the resistance R₁, R₂, or R₃ be infinite.In such a case, the display element LC_((n,m)) can hold chargessemi-permanently. In other words, display can be performedsemi-permanently. In fact, however, these resistance components havefinite values, and leakage current flows through resistors. Accordingly,charges stored in the display element LC_((n,m)) change with time; thus,regular rewriting (or additional writing) is required. A method forstabilizing the potential of the display element LC_((n,m)) is disclosedin Patent Document 1.

In general liquid crystal display devices, rewriting of images isperformed about 60 times per second (60 Hz driving) or more especiallyin the case of displaying a moving image. In that case, the rewriting isperformed every 16.7 milliseconds (one frame). In such frequentrewriting (or short frame period), variation in luminance or the like ofa display element in one frame usually cannot be recognized, and theabove-described variation in the charge stored in the display elementLC_((n,m)) is hardly problematic.

However, such frequent rewriting is not generally needed in the case ofdisplaying a still image. A driver needs to be driven to inject chargesto a display element every time an image is rewritten, which consumespower. A method in which the frequency of rewriting is reduced as muchas possible to reduce power consumption is disclosed in Patent Document2.

A problem in a conventional active matrix liquid crystal display deviceincluding a silicon-based transistor (an amorphous silicon TFT or apolysilicon TFT) was the resistance R₃ in the equivalent circuitillustrated in FIG. 2B. The resistance R₃ which is resistance of thetransistor in an off state (i.e., off-state resistance) was lower thanthe resistance R₁ and the resistance R₂ by several orders or more ofmagnitude.

Thus, charges in a liquid crystal display element could not be held fora long time, and the rewriting frequency could only be reduced to onceper several seconds at most for the following reason: if rewriting isnot performed for a long time, display is greatly deteriorated.

In recent years, research on a transistor using an oxide semiconductorhas been advanced. In such a situation, it was found that off-statecurrent in the transistor using an oxide semiconductor can be reduced tobe lower than that in a silicon-based transistor by several orders ormore of magnitude. Accordingly, the rewriting frequency can be furtherreduced; thus, a still-image display method in which rewriting isperformed at extremely low frequency, for example, once per 100 secondsis considered possible.

[Patent Document 1] U.S. Pat. No. 7,362,304

[Patent Document 2] U.S. Pat. No. 7,321,353

SUMMARY OF THE INVENTION

However, in the case where the cycle of rewriting is longer than orequal to one second, a difference in image data between before and afterrewriting is recognized even if the difference is small (e.g., adifference of 1 grayscale in 64 grayscales), which brings discomfort tousers. In order to prevent such a problem, variation in charge (orvariation in potential) of a liquid crystal display element needs to beless than or equal to 1% between frames (a period between rewriting andthe subsequent rewriting).

In that case, the minimum values of the resistance R₁, the resistanceR₂, and the resistance R₃ need to be increased, or the sum of thecapacitance of the capacitor C_((n,m)) and the capacitance of the liquidcrystal display element LC_((n,m)) needs to be increased.

Off-state current of a transistor using an oxide semiconductor can beextremely small, for example, 1 zA (zeptoampere, 10⁻²¹ A) (in terms ofresistivity, 10²⁰ Ω to 10²¹ Ω which is also extremely high); thus, theresistance R₃ is substantially infinite. In addition, since a dielectricwith high insulating properties can be used as the capacitor, theresistance R₁ is also high. However, it was difficult to increase theresistance R₂ of the liquid crystal display element to 10¹³ Ω or higherfor the following reasons: the resistivity of a liquid crystal materialitself cannot be unlimitedly increased and the electrode area is large.

The area of the capacitor needs to be increased in order to increase thecapacitance; however, increasing the area of the capacitor is restrictedby the size of a pixel. In addition, when the capacitance is large, theamount of charge injected and emitted at the time of rewriting is alsolarge, which increases power consumption.

An object of one embodiment of the present invention is to provide anelectro-optical display device in which variation in charge of a liquidcrystal display element can be suppressed to such a level that rewritingcannot be recognized by the human eye even in the case of performingrewriting at extremely low frequency, once in 100 seconds or less, or adisplay method of the electro-optical display device.

Another object of one embodiment of the present invention is to providean electro-optical display device in which variation in charge (orvariation in potential) of a display element in the longest frame isless than or equal to 1% or a display method of the electro-opticaldisplay device.

Another object of one embodiment of the present invention is to providean electro-optical display device whose power consumption can be reducedor a display method of the electro-optical display device.

Another object of one embodiment of the present invention is to providean electro-optical display device which has excellent displayperformance or a display method of the electro-optical display device.

Another object of one embodiment of the present invention is to providean electro-optical display device which can display a still image withthe number of times of rewriting reduced in order to reduce powerconsumption or a display method of the electro-optical display device.

Another object of one embodiment of the present invention is to providea novel electro-optical display device which can display a still imageand a moving image or a display method of the electro-optical displaydevice.

Before the present invention is described, terms used in thisspecification will be briefly explained. A source and a drain of atransistor have the same or substantially the same structure andfunction. Even if the structures are different, in this specification,when one of a source and a drain of a transistor is called a source, theother is called a drain for convenience, and they are not particularlydistinguished for the reason that a potential applied to the source orthe drain or a polarity of the potential is not definite. Therefore, asource in this specification can be alternatively referred to as adrain.

In this specification, the expression “to be orthogonal to each other(in a matrix)” means not only to intersect with each other at rightangles but also to be orthogonal to each other in the simplest circuitdiagram even though a physical angle is not a right angle. In addition,the expression “to be parallel to each other (in a matrix)” means to beparallel to each other in the simplest circuit diagram even though twowirings are provided so as to physically intersect with each other.

Further, even when the expression “to be connected” is used in thisspecification, there is a case in which no physical connection is madein an actual circuit and a wiring is just extended. For example, in aninsulated-gate field-effect transistor (MISFET) circuit, there is a casein which one wiring serves as gates of a plurality of MISFETs. In thatcase, one wiring may have a plurality of branches to gates in a circuitdiagram. In this specification, the expression “a wiring is connected toa gate” is also used to describe such a case.

One embodiment of the present invention is an electro-optical displaydevice having a pixel including a first transistor, a second transistor,a third transistor, and a display element. A source of the firsttransistor is connected to a gate of the second transistor and a gate ofthe third transistor, a source of the second transistor and a source ofthe third transistor are connected to one electrode of the displayelement, a gate of the first transistor is connected to a scan line, anda drain of the first transistor is connected to a signal line.

Here, the second transistor is an N-channel transistor and the thirdtransistor is a P-channel transistor. Off-state current of the firsttransistor is preferably less than or equal to 1/100 of the leakagecurrent of the display element.

The electro-optical display device may include a capacitor. Thecapacitor is arranged so that one electrode of the capacitor isconnected to the source of the first transistor and the other electrodeis connected to a capacitor line or another wiring. The capacitance ofthe capacitor is preferably less than or equal to 1/10 of thecapacitance of the display element.

Another embodiment of the present invention is a display method of theabove electro-optical display device having a frame which is longer thanor equal to 100 seconds, preferably longer than or equal to 1000seconds. Needless to say, the display method may be a method in whichone or more frames each of which is shorter than 100 seconds and one ormore frames each of which is longer than or equal to 100 seconds,preferably longer than or equal to 1000 seconds are combined.

For example, in successive first to third frames, the first frame, thesecond frame, and the third frame can be set to 16.7 milliseconds, 16.7milliseconds, and 1000 seconds, respectively. Here, in the first frame,so-called overdriving in which an absolute value of potential applied toa display element is set to be larger than that of potentialcorresponding to a certain grayscale to increase the response speed ofthe display element may be performed; in the second frame, an absolutevalue of potential applied to the display element may be set to beslightly smaller than that of the potential corresponding to thegrayscale; and then in the third frame which is long, the potentialcorresponding to the grayscale may be applied to the display element.

Another embodiment of the present invention is a display method of theabove electro-optical display device which has a frame in which timetaken for writing of one screen is shorter than or equal to 0.2milliseconds.

In the above electro-optical display device, a drain of the secondtransistor may be connected to a high potential line. Alternatively, thedrain of the second transistor and the other electrode of the capacitormay be connected to the capacitor line.

In the above electro-optical display device, a drain of the thirdtransistor may be connected to a low potential line. Alternatively, thedrain of the third transistor may be connected to the scan line.

The maximum value of the potential of the high potential line ispreferably higher than or equal to the maximum value of potentialapplied to the one electrode of the display element, and the minimumvalue of the potential of the low potential line is preferably lowerthan or equal to the minimum value of the potential applied to the oneelectrode of the display element.

In the above electro-optical display device, an oxide semiconductor maybe used in any one or two of the first to third transistors. Forexample, an oxide semiconductor may be used in the first transistor andthe second transistor.

Alternatively, a polycrystalline semiconductor or a single crystalsemiconductor may be used in one or both of the second transistor andthe third transistor. As examples of the polycrystalline semiconductor,polycrystalline silicon, polycrystalline silicon germanium, andpolycrystalline germanium are given. As examples of the single crystalsemiconductor, single crystal silicon, single crystal silicon germanium,and single crystal germanium are given.

In particular, in the case where the gate capacitance of each of thesecond transistor and the third transistor is reduced, the secondtransistor and the third transistor are preferably formed using asemiconductor material whose field effect mobility is 10 times or moreas high as that of the first transistor, or a semiconductor materialwhose field effect mobility is higher than or equal to 100 cm²/Vs. Theuse of such a material makes it possible to secure sufficient on-statecurrent even when a channel width is reduced; thus, the area of achannel can be reduced and the gate capacitance can be reduced.

In the case where the second transistor and the third transistor areformed using the above-described material with high field effectmobility, a driver circuit (a shift register or the like) located in theperiphery of the display device may include a transistor using such amaterial.

In the above electro-optical display device, when the first transistoris in an off state (in the case of an N-channel transistor, a statewhere the potential of the gate is lower than the potential of thesource and the potential of the drain), leakage current between thesource and the drain is less than or equal to 1×10⁻²⁰ A, preferably lessthan or equal to 1×10⁻²¹ A at a temperature where the transistor is inuse (e.g., 25° C.), or less than or equal to 1×10⁻²⁰ A at 85° C.

In the case of a general silicon semiconductor, it is difficult torealize leakage current having such a small value; however, in atransistor obtained by processing an oxide semiconductor underpreferable conditions, such a value can be achieved. Thus, an oxidesemiconductor is preferably used as a material of the first transistor.Needless to say, if leakage current can be made to have a value smallerthan or equal to the above-described value by another method with theuse of a silicon semiconductor or other kinds of semiconductors, the useof such semiconductors is not precluded.

Although a variety of known materials can be used as an oxidesemiconductor, the band gap of the material is preferably greater thanor equal to 3 eV, more preferably greater than or equal to 3 eV and lessthan 3.6 eV. In addition, the electron affinity of the material ispreferably greater than or equal to 4 eV, more preferably greater thanor equal to 4 eV and less than 4.9 eV. In particular, an oxide includinggallium and indium is preferable for the purpose of the presentinvention. Among these materials, a material whose carrier concentrationderived from a donor or an acceptor is less than 1×10⁻¹⁴ cm⁻³,preferably less than 1×10⁻¹¹ cm⁻³.

Although there is no limitation on the leakage current between a sourceand a drain of the second transistor or the third transistor in an offstate, leakage current is preferably smaller, in which case powerconsumption can be reduced. Further, in the first to third transistors,gate leakage current (leakage current between the gate and the source orbetween the gate and the drain) needs to be extremely low; also in thecapacitor, internal leakage current (leakage current between theelectrodes) needs to be low. Each leakage current is preferably lessthan or equal to 1×10⁻²⁰ A, more preferably less than or equal to1×10⁻²¹ A at a temperature where the transistor or the capacitor is inuse (e.g., 25° C.).

FIG. 1A illustrates an example of a circuit of a pixel in theelectro-optical display device of one embodiment of the presentinvention. This pixel includes a first transistor (also referred to as aselection transistor) WTr_((n,m)), a second transistor (also referred toas an N-channel driving transistor) NTr_((n,m)), a third transistor(also referred to as a P-channel driving transistor) PTr_((n,m)), acapacitor C_((n,m)), and a display element LC_((n,m)).

A source of the selection transistor WTr_((n,m)) is connected to a gateof the N-channel driving transistor NTr_((n,m)), a gate of the P-channeldriving transistor PTr_((n,m)), and one electrode of the capacitorC_((n,m)). A source of the N-channel driving transistor NTr_((n,m)) anda source of the P-channel driving transistor PTr_((n,m)) are connectedto one electrode of the display element LC_((n,m)).

A gate of the selection transistor WTr_((n,m)) is connected to a scanline X_(n), a drain of the selection transistor WTr_((n,m)) is connectedto a signal line Y_(m), and the other electrode of the capacitorC_((n,m)) is connected to a capacitor line Z_(n). Moreover, a drain ofthe N-channel driving transistor NTr_((n,m)) is connected to a highpotential line U_(n), and a drain of the P-channel driving transistorPTr_((n,m)) is connected to a low potential line W_(n).

Although the N-channel driving transistor NTr_((n,m)) and the P-channeldriving transistor PTr_((n,m)) have a similar structure to a CMOSinverter circuit, they have a different polarity of a power supply fromthe CMOS inverter circuit. An operation example of such a circuit willbe described with reference to FIGS. 3A to 3F. In each of FIGS. 3A to3F, a circle is drawn on a transistor in an on state and a cross mark isdrawn on a transistor in an off state.

Note that specific numeric values of potentials are given below forunderstanding the technical idea of the present invention. Needless tosay, such values are changed depending on a variety of characteristicsof a transistor and a capacitor, or the convenience of a practitioner.

The high potential line U_(n) is held at +5 V, and the low potentialline W_(n) is held at −5 V. A scan pulse and an image signal aresupplied to the scan line X_(n) and the signal line Y_(m), respectively,as in a conventional active matrix liquid crystal display device. Thecapacitor line Z_(n) is held at constant potential (e.g., 0 V).

Further, the N-channel driving transistor NTr_((n,m)) is off (currentdoes not flow) when the potential of the gate is lower than thepotential of the source or the potential of the drain, whichever islower, and is on (current flows) when the potential of the gate is thesame as or higher than the potential of the source or the potential ofthe drain, whichever is lower. Further, the P-channel driving transistorPTr_((n,m)) is off (current does not flow) when the potential of thegate is higher than the potential of the source or the potential of thedrain, whichever is higher, and is on (current flows) when the potentialof the gate is the same as or lower than the potential of the source orthe potential of the drain, whichever is higher.

Such characteristics of the transistors are extremely ideal, that is,the threshold voltages of both the N-channel driving transistorNTr_((n,m)) and the P-channel driving transistor PTr_((n,m)) are 0 V.Here, such ideal transistors are assumed for simplicity of thedescription; however, it is actually necessary to consider thattransistors operate in accordance with their threshold voltages.

In particular, in transistors using a material such as polycrystallinesilicon, variation in threshold voltage is large between thetransistors. When a display device is formed using such transistors withdifferent qualities, display unevenness occurs. In order to solve such aproblem, original display signals are preferably corrected so thatdisplay signals corresponding to respective transistors are input to thetransistors.

Assume that the potential of the source of the N-channel drivingtransistor NTr_((n,m)) (i.e., the potential of the source of theP-channel driving transistor PTr_((n,m)) or the potential of the oneelectrode of the display element LC_((n,m))) is 0 V and that thepotential of the other electrode of the display element LC_((n,m)) isalso 0 V.

The case where data of +5 V is written to this pixel (i.e., thepotential of the one electrode of the display element LC_((n,m)) isincreased to +5 V) is considered. In that case, the potential of thegate of the N-channel driving transistor NTr_((n,m)) (i.e., thepotential of the gate of the P-channel driving transistor PTr_((n,m)))is preferably set at +5 V. In other words, as in the case of normal datawriting of an active matrix liquid crystal display device, the potentialof the scan line X_(n) may be controlled to turn on the selectiontransistor WTr_((n,m)), the potential of the signal line Y_(m) may beset at +5 V, and furthermore the potential of the scan line X_(n) may becontrolled to turn off the selection transistor WTr_((n,m)).

The potential of the source of the selection transistor WTr_((n,m))(i.e., the gate of the N-channel driving transistor NTr_((n,m)) and thegate of the P-channel driving transistor PTr_((n,m))) becomes +5 V, sothat the N-channel driving transistor NTr_((n,m)) is turned on andcurrent flows from the high potential line U_(n) to the source of theN-channel driving transistor NTr_((n,m)). In contrast, the P-channeldriving transistor PTr_((n,m)) is off. Thus, the one electrode of thedisplay element LC_((n,m)) is increased from 0 V to +5 V as illustratedin FIG. 3A.

Next, the case where data of −3 V is written to the pixel is considered.In that case, the potential of the gate of the N-channel drivingtransistor NTr_((n,m)) (i.e., the potential of the gate of the P-channeldriving transistor PTr_((n,m))) is preferably set at −3 V.

The potential of the gate of the P-channel driving transistorPTr_((n,m)) becomes −3 V, so that the P-channel driving transistorPTr_((n,m)) is turned on and current flows from the source of theP-channel driving transistor PTr_((n,m)) to the low potential lineW_(n). In contrast, the N-channel driving transistor NTr_((n,m)) is off.Thus, the potential of the one electrode of the display elementLC_((n,m)) is decreased from +5 V to −3 V as illustrated in FIG. 3B.

Next, the case where data of +2 V is written to the pixel is considered.In that case, the potential of the gate of the N-channel drivingtransistor NTr_((n,m)) (i.e., the potential of the gate of the P-channeldriving transistor PTr_((n,m))) is preferably set at +2 V.

The potential of the gate of the N-channel driving transistorNTr_((n,m)) becomes +2 V, so that the N-channel driving transistorNTr_((n,m)) is turned on and current flows from the high potential lineU_(n) to the source of the N-channel driving transistor NTr_((n,m)). Incontrast, the P-channel driving transistor PTr_((n,m)) is off. Thus, thepotential of the one electrode of the display element LC_((n,m)) isincreased from −3 V to +2 V as illustrated in FIG. 3C.

Next, the case where data of −5 V is written to the pixel is considered.In that case, the potential of the gate of the N-channel drivingtransistor NTr_((n,m)) (i.e., the potential of the gate of the P-channeldriving transistor PTr_((n,m)) is preferably set at −5 V.

The potential of the gate of the P-channel driving transistorPTr_((n,m)) becomes −5 V, so that the P-channel driving transistorPTr_((n,m)) is turned on and current flows from the source of theP-channel driving transistor PTr_((n,m)) to the low potential lineW_(n). In contrast, the N-channel driving transistor NTr_((n,m)) is off.Thus, the potential of the one electrode of the display elementLC_((n,m)) is decreased from +2 V to −5 V as illustrated in FIG. 3D.

Described above is AC driving in which the polarity of the potential ofthe pixel is inverted every time data rewriting is performed; however,the potential can be changed with the polarity kept the same. Next, thecase where data of −3 V is written to the pixel in the state of FIG. 3Dis considered. In that case, the potential of the gate of the N-channeldriving transistor NTr_((n,m)) (i.e., the potential of the gate of theP-channel driving transistor PTr_((n,m))) is preferably set at −3 V.

The potential of the gate of the N-channel driving transistorNTr_((n,m)) becomes −3 V, so that the N-channel driving transistorNTr_((n,m)) is turned on and current flows from the high potential lineU_(n) to the source of the N-channel driving transistor NTr_((n,m)). Incontrast, the P-channel driving transistor PTr_((n,m)) is off. Thus, thepotential of the one electrode of the display element LC_((n,m)) isincreased from −5 V to −3 V as illustrated in FIG. 3E.

Next, the case where data of −4 V is written to the pixel is considered.In that case, the potential of the gate of the N-channel drivingtransistor NTr_((n,m)) (i.e., the potential of the gate of the P-channeldriving transistor PTr_((n,m)) is preferably set at −4 V.

The potential of the gate of the P-channel driving transistorPTr_((n,m)) becomes −4 V, so that the P-channel driving transistorPTr_((n,m)) is turned on and current flows from the source of theP-channel driving transistor PTr_((n,m)) to the low potential lineW_(n). In contrast, the N-channel driving transistor NTr_((n,m)) is off.Thus, the potential of the one electrode of the display elementLC_((n,m)) is decreased from −3 V to −4 V as illustrated in FIG. 3F.

In such a manner, the potential of the display element LC_((n,m)) iscontrolled, whereby image display can be performed with the use ofanalog signals. By applying the above-described method, display can beperformed with one frame of 16.7 milliseconds, which is substantiallythe same as in a normal liquid crystal display device. When one frame isset longer than or equal to 100 seconds, preferably longer than or equalto 1000 seconds, power consumption in still-image display can bereduced.

Here, it is important to stabilize the potential of the gate of theN-channel driving transistor NTr_((n,m)) (i.e., the potential of thegate of the P-channel driving transistor PTr_((n,m))) in order to reducevariation in the potential of the one electrode of the display elementLC_((n,m)) for the following reason: potential corresponding to thepotential of the gate of the N-channel driving transistor NTr_((n,m))(i.e., the potential of the gate of the P-channel driving transistorPTr_((n,m))) is applied to the one electrode of the display elementLC_((n,m)).

Although the resistance of the display element LC_((n,m)) is preferablyhigh, the resistance is finite, which causes moderate leakage current.For example, in FIG. 3F, the potential of the one electrode of thedisplay element LC_((n,m)) is −4 V. If there are no factors, thepotential of the one electrode of the display element LC_((n,m)) movesto 0 V as close as possible. In the circuit illustrated in FIG. 1A, whenthe potential of the one electrode of the display element LC_((n,m))moves to be larger than −4 V even slightly, charges immediately transferthrough the P-channel driving transistor PTr_((n,m)) in an on state, sothat the potential automatically goes back to −4 V.

The above effect allows display to be maintained for a long time withoutdeterioration. Needless to say, although high resistance of the displayelement LC_((n,m)) in the circuit illustrated in FIG. 1A is effective inreducing power consumption, display deterioration does not occur even ifthe resistance is not quite high.

On the other hand, the variation in the potential of the gate of theN-channel driving transistor NTr_((n,m)) (i.e., the potential of thegate of the P-channel driving transistor PTr_((n,m))) needs to beavoided as much as possible for the following reason: the potential ofthe one electrode of the display element LC_((n,m)) is automaticallydetermined in accordance with the potential of the gate of the N-channeldriving transistor NTr_((n,m)) (i.e., the potential of the gate of theP-channel driving transistor PTr_((n,m))) as described above.

Here, when the off-state resistance of the selection transistorWTr_((n,m)) is sufficiently high, the variation in the potential of thegate of the N-channel driving transistor NTr_((n,m)) (i.e., thepotential of the gate of the P-channel driving transistor PTr_((n,m)))is extremely small. For example, in the case where the sum ofcapacitance of the capacitor C_((n,m)) and parasitic capacitance ofother parts is set to 100 fF which is 1/20 of the capacitance of atypical liquid crystal display element and the sum of resistance ofoff-state resistance of the selection transistor WTr_((n,m)), parasiticresistance of the capacitor C_((n,m)), parasitic resistance between thegate and the source of the N-channel driving transistor NTr_((n,m)), andparasitic resistance between the gate and the source of the P-channeldriving transistor PTr_((n,m)) is set to 10²⁰ Ω, the time constant of acircuit formed using the capacitance of the capacitor C_((n,m)) and thelike and the above resistance is 10⁷ seconds.

This means that the variation in the potential at the point where 100seconds have passed is 0.001%, and the variation in the potential is0.01% even at the point where 1000 seconds have passed. Thus, even ifone frame is longer than or equal to 100 seconds, preferably longer thanor equal to 1000 seconds, variation in the potential of the displayelement can be less than or equal to 1%, and a difference in displaybetween before and after rewriting even having such a long period cannotbe recognized.

Needless to say, an increase in the capacitance of the capacitorC_((n,m)) allows the variation in the potential to be suppressed for alonger time. However, the increase in the capacitance of the capacitorC_((n,m)) causes an increase in power consumption during rewriting.Further, increasing the area of the capacitor C_((n,m)) or reducing thedistance between electrodes in order to increase the capacitance is notpreferable because leakage current is increased.

Further, large capacitance impairs rewriting at an extremely high speed,which is described later, in some cases. Thus, the capacitance ispreferably greater than or equal to 1 fF and less than 1 pF, morepreferably greater than or equal to 5 fF and less than 200 fF. Suchcapacitance does not impair the implementation of the present inventionat all due to the characteristic of the circuit.

Note that the capacitance here includes, in its category, the gatecapacitance of the N-channel driving transistor NTr_((n,m)), the gatecapacitance of the P-channel driving transistor PTr_((n,m)), and thelike. Thus, the capacitor C_((n,m)) does not particularly need to beprovided as long as such capacitance has a certain amount. In the casewhere the capacitor C_((n,m)) is not provided, a capacitor line neededfor the capacitor C_((n,m)) can be omitted.

Note that by making the capacitance of the capacitor C_((n,m)) and thelike sufficiently small as described above, driving can also beperformed at a high speed. Thus, writing is performed for a short timein one frame and a driver circuit needed for writing is stopped duringthe most of the time in the one frame, whereby power consumption can bereduced. In addition, image display, in particular, display of a movingimage at a high speed can be improved.

In a normal active matrix liquid crystal display device, most of thetime in one frame is spent for writing of one screen. In the case whereone frame is, for example, 16.7 milliseconds, writing (rewriting) to anyof rows is performed during most of the time in the frame. In such asituation, power is constantly supplied to the driver circuit.

In a driver, a CMOS inverter circuit or the like is usually used. Sincepower supply voltage is supplied to the driver, through current isgenerated in an inverter; thus, power is consumed.

In order to reduce the power consumption, the driver is stopped as muchas possible in one frame to stop power supply to the driver. For thatpurpose, time necessary for writing (rewriting) of one screen ispreferably reduced. In other words, the time necessary for writing maybe set to be shorter than 2 milliseconds or less than 10% of one frame,whichever is shorter, and if possible, shorter than 0.2 milliseconds orless than 1% of one frame, whichever is shorter. The driver circuit maybe stopped in the rest of the time.

Note that not all driver circuits need to be stopped here, and at leasta circuit which supplies a signal to the scan line or the signal linemay be stopped during the above-described period. Needless to say, whena larger number of circuits are stopped, power consumption can bereduced more.

Under the above condition, in the case where one frame is, for example,16.7 milliseconds, a display signal is not supplied to the signal linein 90% or more of the frame, and time for image writing (rewriting) isless than 10% of the frame, that is, shorter than 1.67 milliseconds,preferably shorter than 0.17 milliseconds.

Further, in the case where one frame is 33.3 milliseconds, a displaysignal is not supplied to the signal line for longer than or equal to31.3 milliseconds, and the time for which a display signal is applied tothe signal line is shorter than 2 milliseconds, preferably shorter than0.2 milliseconds.

For example, in the case where a potential difference between the sourceand the drain and a potential difference between the gate and the sourceare set to +5 V and +10 V, respectively in the selection transistorWTr_((n,m)) which has a field effect mobility of 11 cm²/Vs, a channellength of 2 μm, a channel width of 20 μm, a thickness of a gateinsulating film (silicon oxide) of 30 nm, and a threshold voltage of 0V, current between the source and the drain and on-state resistivity arecalculated to be approximately 0.5 mA and 10 kΩ, respectively.

In addition, the time constant in the case where the capacitance(including parasitic capacitance) of the capacitor C_((n,m)) and thelike is 100 fF is 1 nanosecond (100 fF×10 kΩ), and 100 nanoseconds issufficient for data writing. If the number of rows in a matrix of thedisplay device is 1000, the time necessary for rewriting of one screenis 0.1 millisecond, which is 1000 times as long as 100 nanoseconds, andthe above condition is satisfied.

In order to achieve such a high-speed operation, the capacitance of thecapacitor C_((n,m)) is preferably less than 200 fF. The capacitance ofthe capacitor C_((n,m)) is a factor in determining time for which thepotential of the gate of the N-channel driving transistor NTr_((n,m)) isheld, and can be determined independently of the capacitance of theliquid crystal display element LC_((n,m)).

Thus, if the time for which the potential of the gate of the N-channeldriving transistor NTr_((n,m)) is held is enough, the capacitance of thecapacitor C_((n,m)) is preferably reduced as much as possible. In thisregard, the electro-optical display device of the present invention isdifferent from a conventional active matrix display device in which thecapacitance of a capacitor is determined depending on the capacitance ofa liquid crystal display element.

Note that according to the characteristics of the circuit illustrated inFIG. 1A, the gate capacitance of the N-channel driving transistorNTr_((n,m)) and the gate capacitance of the P-channel driving transistorPTr_((n,m)) are also parasitic capacitance parallel to the capacitanceof the capacitor C_((n,m)). It is effective to reduce the channel areasof the N-channel driving transistor NTr_((n,m)) and the P-channeldriving transistor PTr_((n,m)) in order to reduce such parasiticcapacitance.

For that purpose, it is preferable that polycrystalline silicon orsingle crystal silicon with high field effect mobility be used for theN-channel driving transistor NTr_((n,m)) and the P-channel drivingtransistor PTr_((n,m)) and that the channel width of each of thetransistor be set to 1/50 to ⅕ of the channel width of the selectiontransistor WTr_((n,m)). Even when the channel width is set to, forexample, 1/10 of the channel width of the selection transistorWTr_((n,m)), the operation of the display device has little problem.

Note that, although one frame is set to 16.7 milliseconds or 33.3milliseconds in the above example, an effect of a reduction in powerconsumption can be obtained by stopping at least part of a drivercircuit even in the case where a still image is displayed with one frameof 100 seconds or 1000 seconds.

Some examples are described above as embodiments of the presentinvention. However, it is obvious, from the technical idea of thepresent invention, that other modes which can achieve at least one ofthe objects are also possible without limitation to the above examples.

As is clear from the above description, even when rewriting is performedevery 100 seconds or longer, variation in potential of a display elementcan be as small as 1% or less. As a result, deterioration of display canbe reduced to such a level that a difference in display between beforeand after rewriting cannot be recognized.

Further, the method described above, in which rewriting of one screen isperformed by spending extremely short time of 0.2 milliseconds orshorter in one frame, for example, 0.17 milliseconds in the frame andthe image is held during the rest of the frame, is similar to the methodfor images on a film.

It is preferable that such characteristics be applied to athree-dimensional (3D) image display method of a frame sequential type,in which high-speed shutters are used. In such a 3D image displaymethod, an image for the left eye and an image for the right eye areswitched at a high speed, and right-and-left shutters of a pair of 3Dglasses are switched corresponding to the images. For example, whenpeople see an image for the right eye, the shutter for the right eyeopens so people can see the image. The image is preferably completedsubstantially at this point.

A commercially available liquid crystal display device of a framesequential type employs 240 Hz driving. The mechanism of the 240 Hzdriving is as follows: an image for the left eye is completed in 1/240seconds, a shutter for the left eye opens for the subsequent 1/240seconds, an image for the right eye is completed in the subsequent 1/240seconds, and a shutter for the right eye opens for the subsequent 1/240seconds. In other words, the period in which the left eye sees the imageis ¼ of the total, which causes people to see darkness in the image.Thus, a screen needs to be brightened than usual; however, needless tosay, this causes an increase in power consumption.

This problem can be solved by increasing the time for which the shutteropens. The above-described characteristic in which image rewriting canbe performed by spending 10% or less of one frame, or shorter than orequal to 2 milliseconds is suitable for the purpose.

Furthermore, in a liquid crystal display device which needs to performimage writing at such a high speed, a liquid crystal exhibiting a bluephase as a liquid crystal phase is preferably used. However, theblue-phase liquid crystal has a problem in that the resistance is lowerthan that of general liquid crystal materials.

Due to the above problem, once still image display is performed with oneframe of several seconds or longer by the method disclosed in PatentDocument 2, display is deteriorated even though moving image display isperformed without any problem. In contrast, when one embodiment of thepresent invention is applied to a blue-phase liquid crystal, displaydeterioration due to leakage current by the blue-phase liquid crystalcan be sufficiently suppressed.

In other words, when one of the embodiments of the present invention isapplied to the blue phase liquid crystal, excellent moving image display(including 3D image display of a frame sequential type) can beperformed. In addition, a liquid crystal display device in which powerconsumption in still-image display is low can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B illustrate examples of circuits of an electro-opticaldisplay device of the present invention.

FIGS. 2A and 2B illustrate examples of circuits of a conventionalelectro-optical display device.

FIGS. 3A to 3F illustrate examples of driving methods of a circuit of anelectro-optical display device of the present invention.

FIGS. 4A and 4B illustrate examples of circuits of an electro-opticaldisplay device of the present invention.

FIGS. 5A and 5B illustrate examples of circuits of an electro-opticaldisplay device of the present invention.

FIGS. 6A and 6B illustrate examples of circuits of an electro-opticaldisplay device of the present invention.

FIGS. 7A and 7B illustrate examples of circuits of an electro-opticaldisplay device of the present invention.

FIGS. 8A and 8B illustrate examples of circuits of an electro-opticaldisplay device of the present invention.

FIGS. 9A and 9B illustrate examples of circuits of an electro-opticaldisplay device of the present invention.

FIG. 10 illustrates an example of a circuit of an electro-opticaldisplay device of the present invention.

FIGS. 11A and 11B illustrate examples of circuits of an electro-opticaldisplay device of the present invention.

FIGS. 12A to 12E illustrate an example of a manufacturing process of anelectro-optical display device of the present invention.

FIGS. 13A to 13E illustrate an example of a manufacturing process of anelectro-optical display device of the present invention.

FIGS. 14A and 14B each illustrate an example of circuit arrangement ofan electro-optical display device of the present invention.

FIGS. 15A and 15B each illustrate an example of circuit arrangement ofan electro-optical display device of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, the Embodiments will be described with reference to theaccompanying drawings. Note that the Embodiments can be carried out inmany different modes, and it is easily understood by those skilled inthe art that modes and details can be modified in various ways withoutdeparting from the spirit and scope of the present invention. Therefore,the present invention should not be construed as being limited to thedescription of the embodiments below.

The structures, the conditions, and the like disclosed in any of thefollowing Embodiments can be combined with each other as appropriate.Note that in structures described below, the same portions or portionshaving similar functions are denoted by the same reference numerals indifferent drawings, and detailed description thereof is not repeated insome cases.

Note that in this specification, in referring to a specific row, column,or position in a matrix, reference signs with coordinates such as a“selection transistor WTr_((n,m))” and a “scan line X_(m)” are used. Inparticular, in the case where a row, a column, or a position is notspecified or the case where elements are collectively referred to, thefollowing expressions may be used: a “selection transistor WTr”and a“scan line X”, or simply a “selection transistor” and a “scan line”.

Further, in FIGS. 1A and 1B, FIGS. 2A and 2B, FIGS. 3A to 3F, FIGS. 4Aand 4B, FIGS. 5A and 5B, FIGS. 6A and 6B, FIGS. 7A and 7B, FIGS. 8A and8B, FIGS. 9A and 9B, FIG. 10, and FIGS. 11A and 11B, unless otherwisespecified, reference numerals X_(n), X_(n+1), X_(2n), X_(2n+1), X_(2n+2)refer to scan lines; Y_(m), a signal line; Z_(n), Z_(n+1), and Z_(m),capacitor lines; U_(n), U_(n+1), and U_(m), high potential lines; W_(n),W_(n+1), and W_(m), low potential lines; WTr_((n,m)), a selectiontransistor; NTr_((n,m)), an N-channel driving transistor; PTr_((n,m)), aP-channel driving transistor; C_((n,m)), a capacitor; and LC_((n,m)), adisplay element.

EMBODIMENT 1

In this embodiment, an electro-optical display device illustrated inFIG. 1B will be described. The electro-optical display deviceillustrated in FIG. 1B is obtained by modifying the electro-opticaldisplay device illustrated in FIG. 1A. The difference between FIG. 1Aand FIG. 1B lies in that a capacitor line is orthogonal to a scan line(the capacitor line is parallel to a signal line) in FIG. 1B, while thecapacitor line is parallel to the scan line in FIG. 1A.

With this structure, the signal line does not cross the capacitor line.Thus, parasitic capacitance caused by the crossing can be reduced andattenuation of a display signal can be suppressed.

The electro-optical display device of this embodiment can be driven by amethod the same as that in FIGS. 3A to 3F.

EMBODIMENT 2

In this embodiment, electro-optical display devices illustrated in FIGS.4A and 4B will be described. The electro-optical display deviceillustrated in FIG. 4A is obtained by modifying the electro-opticaldisplay device illustrated in FIG. 1A. The electro-optical displaydevice illustrated in FIG. 4B is obtained by modifying theelectro-optical display device illustrated in FIG. 1B. The differencebetween FIG. 1A and FIG. 4A (or the difference between FIG. 1B and FIG.4B) lies in that a high potential line and a low potential line areorthogonal to a scan line (the high potential line and the low potentialline are parallel to a signal line) in FIG. 4A (or FIG. 4B), while thehigh potential line and the low potential line are parallel to the scanline in FIG. 1A (or FIG. 1B).

With this structure, the signal line does not cross the high potentialline and the low potential line. Thus, parasitic capacitance caused bythe crossing can be reduced and attenuation of a display signal can besuppressed.

The electro-optical display device of this embodiment can be driven by amethod the same as that in FIGS. 3A to 3F.

EMBODIMENT 3

In this embodiment, electro-optical display devices illustrated in FIGS.5A and 5B and FIGS. 6A and 6B will be described. The electro-opticaldisplay devices illustrated in FIGS. 5A and 5B are obtained by modifyingthe electro-optical display devices illustrated in FIGS. 1A and 1B,respectively. The electro-optical display devices illustrated in FIGS.6A and 6B are obtained by modifying the electro-optical display devicesillustrated in FIGS. 4A and 4B, respectively.

The difference between FIG. 1A and FIG. 5A (or between FIG. 1B and FIG.5B, between FIG. 4A and FIG. 6A, and between FIG. 4B and FIG. 6B) liesin that a capacitor line is substituted for a high potential line inFIG. 5A (FIG. 5B, FIG. 6A, and FIG. 6B), while the high potential lineis provided in FIG. 1A (FIG. 1B, FIG. 4A, and FIG. 4B).

With this structure, the number of total wirings can be reduced and anaperture ratio of a pixel can be increased. For example, in the case ofa matrix having N rows and M columns (N and M are each a natural numbergreater than or equal to 2), the display devices having the circuitconfigurations of FIG. 5A and FIG. 5B have (3N+M) wirings and (2N+2M)wirings, respectively, while the display devices having the circuitconfigurations of FIG. 1A and FIG. 1B have (4N+M) wirings and (3N+2M)wirings, respectively. Thus, the number of wirings in FIG. 5A can besmaller by N than that in FIG. 1A; the number of wirings in FIG. 5B canbe smaller by N than that in FIG. 1B.

Further, in FIG. 5A, the number of wirings crossed by a signal line canbe reduced, which allows a reduction in parasitic capacitance andsuppression of attenuation of a display signal.

Note that in this embodiment, it is preferable that the maximum value ofthe potential of the capacitor line be greater than or equal to themaximum value of the potential applied to one electrode of a displayelement. Other than that, the electro-optical display device of thisembodiment can be driven by a method the same as that in FIGS. 3A to 3F.

EMBODIMENT 4

In this embodiment, electro-optical display devices illustrated in FIGS.7A and 7B will be described. The electro-optical display devicesillustrated in FIGS. 7A and 7B are obtained by modifying theelectro-optical display devices illustrated in FIG. 1A and FIG. 4A,respectively.

The difference between FIG. 1A and FIG. 7A (or between FIG. 4A and FIG.7B) lies in that a scan line X_(n+1) in the subsequent row issubstituted for a capacitor line in FIG. 7A (or FIG. 7B), while thecapacitor line is provided in FIG. 1A (or FIG. 4A).

With this structure, the number of total wirings can be reduced and anaperture ratio of a pixel can be increased. For example, in the case ofa matrix having N rows and M columns (N and M are each a natural numbergreater than or equal to 2), the display devices having the circuitconfigurations of FIGS. 7A and 7B have (3N+M+1) wirings and (2N+3M+1)wirings, respectively, while the display devices having the circuitconfigurations of FIG. 1A and FIG. 4A have (4N+M) wirings and (2N+3M)wirings, respectively. Thus, the number of wirings in FIG. 7A can besmaller by N−1 than that in FIG. 1A; the number of wirings in FIG. 7Bcan be smaller by N−1 than that in FIG. 4A.

Further, in FIG. 7A, the number of wirings crossed by a signal line canbe reduced, which allows a reduction in parasitic capacitance andsuppression of attenuation of a display signal.

The electro-optical display devices of this embodiment can be driven bya method the same as that in FIGS. 3A to 3F.

EMBODIMENT 5

In this embodiment, electro-optical display devices illustrated in FIGS.8A and 8B and electro-optical display devices illustrated in FIGS. 9Aand 9B will be described. The electro-optical display devicesillustrated in FIGS. 8A and 8B are obtained by modifying theelectro-optical display devices illustrated in FIGS. 1A and 1B,respectively. The electro-optical display devices illustrated in FIGS.9A and 9B are obtained by modifying the electro-optical display devicesillustrated in FIGS. 5A and 5B, respectively.

The difference between FIG. 1A and FIG. 8A (between FIG. 1B and FIG. 8B,between FIG. 5A and FIG. 9A, or between FIG. 5B and FIG. 9B) lies inthat a scan line X_(n+1) in the subsequent row is substituted for a lowpotential line in FIG. 8A (FIG. 8B, FIG. 9A, or FIG. 9B), while the lowpotential line is provided in FIG. 1A (FIG. 1B, FIG. 5A, or FIG. 5B).

With this structure, the number of total wirings can be reduced and anaperture ratio of a pixel can be increased. For example, in the case ofa matrix having N rows and M columns (N and M are each a natural numbergreater than or equal to 2), the display devices having the circuitconfigurations of FIGS. 8A and 8B have (3N+M+1) wirings and (2N+2M+1)wirings, respectively, while the display devices having the circuitconfigurations of FIGS. 1A and 1B have (4N+M) wirings and (3N+2M)wirings, respectively. Thus, the number of wirings in FIG. 8A can besmaller by N−1 than that in FIG. 1A; the number of wirings in FIG. 8Bcan be smaller by N−1 than that in FIG. 1B.

Further, in FIG. 8A, the number of wirings crossed by a signal line canbe reduced, which allows a reduction in parasitic capacitance andsuppression of attenuation of a display signal.

It is preferable that a selection transistor in each of theelectro-optical display devices of this embodiment be an N-channeltransistor. In that case, the scan line is designed so that the scanline has potential whose value is less than or equal to the minimumvalue of potential applied to one electrode of a display element, andthus is suitable for being used as the low potential line. Thus, theelectro-optical display device of this embodiment can be driven by amethod the same as that in FIGS. 3A to 3F.

EMBODIMENT 6

In this embodiment, an electro-optical display device illustrated inFIG. 10 will be described. The electro-optical display deviceillustrated in FIG. 10 is obtained by modifying the electro-opticaldisplay device illustrated in FIG. 1A. In FIG. 10, the capacitor lineand the high potential line are shared by adjacent rows, and the lowpotential line is shared by adjacent rows. With such a structure, thenumber of total wirings can be reduced and an aperture ratio of a pixelcan be increased.

Further, the number of wirings crossed by a signal line can be reduced,which allows a reduction in parasitic capacitance and suppression ofattenuation of a display signal.

The electro-optical display device of this embodiment can be driven by amethod the same as that in FIGS. 3A to 3F.

EMBODIMENT 7

In this embodiment, electro-optical display devices illustrated in FIGS.11A and 11B will be described. The electro-optical display devicesillustrated in FIGS. 11A and 11B are obtained by modifying theelectro-optical display devices illustrated in FIGS. 9A and 9B,respectively.

The difference between FIG. 9A and FIG. 11A (or between FIG. 9B and FIG.11B) lies in that a drain of a P-channel driving transistor is connectedto a scan line X_(n) in the row in FIG. 11A (or FIG. 11B), while thedrain of the P-channel driving transistor is connected to a scan lineX_(n+1) in the subsequent row in FIG. 9A (or FIG. 9B).

It is preferable that a selection transistor in each of theelectro-optical display devices of this embodiment be an N-channeltransistor. In that case, the scan line is designed so that the scanline has potential whose value is less than or equal to the minimumvalue of potential applied to one electrode of a display element, andthus is suitable for being connected to the drain of the P-channeldriving transistor (i.e., being used as a low potential line).

Note that, although the P-channel driving transistor is on and the scanline X_(n) is in a high potential state (in the case where the selectiontransistor is an N-channel transistor) when data is written, the scanline X_(n) is in a low potential state when the data writing isfinished; thus, in some cases, the potential of a gate of the P-channeldriving transistor is greatly varied due to variation in the potentialof the scan line. In order to avoid such an influence, the capacitanceof a capacitor is preferably set to be greater than or equal to 10 timesas high as the gate capacitance of the P-channel driving transistor.

EMBODIMENT 8

In this embodiment, an example of a manufacturing method of theelectro-optical display devices described in Embodiments 1 to 7 will bedescribed. Although FIGS. 12A to 12E are cross-sectional viewsillustrating a manufacturing process of this embodiment, theyconceptually illustrate a manufacturing process and does not illustratea particular cross section.

First, an appropriate substrate 101 made of glass or another material isprepared. A surface of the substrate 101 may be coated with a coveringfilm such as a silicon oxide film, a silicon nitride film, an aluminumoxide film, or an aluminum nitride film.

Next, a crystalline semiconductor covering film of polycrystallinesilicon, single crystal silicon, or the like is formed over thesubstrate 101 and is processed into island-shaped semiconductor regions102 a and 102 b. The island-shaped semiconductor regions 102 a and 102 bare used in an N-channel driving transistor and a P-channel drivingtransistor, respectively. Thus, an appropriate amount of donor oracceptor corresponding to each of the N-channel driving transistor andthe P-channel driving transistor may be added. For example, a smallamount of boron may be added to the island-shaped semiconductor region102 a to be a P-type semiconductor with low conductivity, and a smallamount of phosphorus may be added to the island-shaped semiconductorregion 102 b to be an N-type semiconductor with low conductivity.

Furthermore, an insulating film 103 of silicon oxide or the like isformed so as to cover the island-shaped semiconductor regions 102 a and102 b. The insulating film 103 may be a multilayer of materials and mayinclude an amorphous film with high dielectric constant such as analuminum oxide film, a lanthanum oxide film, or a hafnium oxide film.The insulating film 103 serves as a gate insulating film in theN-channel driving transistor and the P-channel driving transistor.

The thickness of the insulating film 103 may be determined asappropriate. However, if the thickness is too small, leakage current isincreased to adversely affect the display performance of theelectro-optical display device, whereas if the thickness is too large,the characteristics of the N-channel driving transistor and theP-channel driving transistor are deteriorated. Thus, the thickness ofthe insulating film 103 is preferably 10 nm to 50 nm, more preferably 20nm to 30 nm. The insulating film 103 may be formed by a plasma CVDmethod, a low-pressure CVD method, or the like. FIG. 12A illustrates thestate up to this point.

Next, a single-layer metal film or a multilayer metal film is formed andprocessed into wirings 104 a and 104 b. Sidewalls may be formed on sidesurfaces of the wirings 104 a and 104 b as illustrated in FIG. 12B. InFIG. 12B, three cross sections of the wiring 104 b correspond to crosssections of three parts of the wiring 104 b. In addition, the wiring 104a is used as, for example, part of a signal line in some cases.

A material which forms an ohmic contact with an oxide semiconductor tobe formed later is preferable as a material of the wirings 104 a and 104b. An example of such a material is a material whose work function W isalmost the same as or smaller than electron affinity φ (an energy gapbetween the lowest end of the conduction band of the oxide semiconductorand the vacuum level) of the oxide semiconductor. In other words,W<φ+0.3 [eV] is satisfied. As examples of the material, titanium,molybdenum, and titanium nitride are given.

Further, the wiring 104 b also serves as gates of the N-channel drivingtransistor and the P-channel driving transistor; thus, a material whichhas an appropriate physical property value such as a work function ispreferable for determining the threshold voltage of the transistors.When these conditions are not satisfied by one material, a multilayerfilm may be formed so that each condition is satisfied by each film. Forexample, a multilayer film of a titanium nitride film and a tantalumnitride film may be used as the wirings 104 a and 104 b.

Although the example in which the same wiring is used as the gates ofthe N-channel driving transistor and the P-channel driving transistor isillustrated in FIG. 12B, the gates may be formed using differentmaterials in order to specifically control the threshold voltages.

After that, an impurity serving as a donor or an acceptor is added by aknown doping technique, so that N-type regions 105 a are formed in theisland-shaped semiconductor region 102 a and P-type regions 105 b areformed in the island-shaped semiconductor region 102 b. The N-typeregions 105 a serve as a source and a drain of the N-channel drivingtransistor. The P-type regions 105 b serve as a source and a drain ofthe P-channel driving transistor. Regions with different dopantconcentrations may be formed in each of the N-type region 105 a and theP-type region 105 b. For example, the dopant concentrations of regionscloser to the wirings 104 a and 104 b may be 1% to 10% of those of otherregions. FIG. 12B illustrates the state up to this point.

After that, heat treatment at 250° C. to 450° C. is preferably performedin a hydrogen atmosphere so that a state of an interface between theinsulating film 103 and each of the island-shaped semiconductor regions102 a and 102 b is improved. It is preferable to perform oxygen plasmatreatment after this heat treatment so that the hydrogen concentrationof an exposed portion of the insulating film 103 is particularlyreduced. The hydrogen concentration in the insulating film 103 may belower than 1×10¹⁸ cm⁻³, preferably lower than 1×10¹⁶ cm⁻³.

Note that surfaces of the wirings 104 a and 104 b are oxidized by theoxygen plasma treatment. The surfaces of the wirings 104 a and 104 b inthis state each have a contact failure with an oxide semiconductor whichis formed later; thus, the oxidized portions are preferably removedafter the oxygen plasma treatment. Typically, a so-called reversesputtering method may be used.

Next, an oxide semiconductor film is formed to a thickness of 3 nm to 30nm by a sputtering method. A method other than a sputtering method maybe employed as a formation method of the oxide semiconductor film. Theoxide semiconductor preferably contains gallium and indium. The hydrogenconcentration in the oxide semiconductor film may be lower than 1×10¹⁸cm⁻³, preferably lower than 1×10¹⁶ cm⁻³ in order that the reliability ofa semiconductor memory device is increased. The composition ratio ofgallium to indium (i.e., gallium/indium) is greater than or equal to 0.5and less than 2, preferably greater than or equal to 0.9 and less than1.2. The oxide semiconductor may contain zinc in addition to gallium andindium.

This oxide semiconductor film is etched, so that an island-shaped oxidesemiconductor region 106 is formed. It is preferable to perform heattreatment on the oxide semiconductor region 106 so that thesemiconductor characteristics are improved. The same effect can also beobtained by performing oxygen plasma treatment. The heat treatment andthe oxygen plasma treatment may be performed separately or at the sametime. Thus, a structure in which the wirings 104 a and 104 b are incontact with the oxide semiconductor region 106 can be obtained.

After that, an insulating film 107 is formed by a known depositionmethod such as a sputtering method. For the purpose of reducing leakagecurrent, the thickness of the insulating film 107 is preferably greaterthan or equal to 10 nm, and the hydrogen concentration in the insulatingfilm 107 is preferably lower than 1×10¹⁸ cm⁻³, more preferably lowerthan 1×10¹⁶ cm⁻³. In order to obtain such a hydrogen concentration, heattreatment, chlorine plasma treatment, or oxygen plasma treatment ispreferably performed. In addition, in order to improve thecharacteristics of the oxide semiconductor region 106, heat treatmentmay also be performed after the insulating film 107 is formed.

Silicon oxide, aluminum oxide, hafnium oxide, lanthanum oxide, aluminumnitride, or the like may be used for the insulating film 107.Alternatively, a composite oxide having a band gap greater than or equalto 6 eV and less than or equal to 8 eV, such as a composite oxide ofaluminum and gallium (the ratio of aluminum to gallium (i.e.,aluminum/gallium) is preferably greater than or equal to 0.5 and lessthan or equal to 3), may be used. A multilayer film of these materialsmay be used as well as a single-layer film thereof.

The insulating film 107 serves as a gate insulating film of a selectiontransistor. In addition, the insulating film 107 serves as a dielectricof a capacitor in many cases.

On the other hand, the insulating film 107 also serves as an interlayerinsulator at an intersection between a signal line and a scan line;thus, a material and a thickness suitable for these purposes need to beselected. In general, in the case where the insulating film 107 is usedas an interlayer insulator, the insulating film 107 preferably has alarge thickness and low dielectric constant, while in the case where theinsulating film 107 is used as a gate insulating film, the insulatingfilm 107 preferably has a small thickness and high dielectric constant.It is difficult to achieve such contradicting purposes with onematerial; thus, a thick film with low dielectric constant may beadditionally provided in part of the insulating film 107, which is usedas an interlayer insulator. FIG. 12C illustrates the state up to thispoint.

After that, wirings 108 a, 108 b, 108 c, and 108 d are formed of aconductive material. The wirings 108 a, 108 b, 108 c, and 108 d eachserve as a gate of the selection transistor or an electrode connected toa source or a drain of the N-channel driving transistor or the P-channeldriving transistor. In addition, the wiring 108 a serves as a scan line.

It is preferable that in each of the wirings 108 a, 108 b, 108 c, and108 d, a material used in a portion in contact with the oxidesemiconductor have a work function higher than the electron affinity ofthe oxide semiconductor by 0.5 eV or more. As examples of such amaterial, tungsten, gold, platinum, p-type silicon, and the like aregiven. Needless to say, a material having lower resistance may beprovided in an upper layer in order to increase conductivity. FIG. 12Dillustrates the state up to this point.

After that, an interlayer insulator 109 which is formed of asingle-layer insulating film or a multilayer insulating film and has aflat surface is formed. The interlayer insulator 109 is selectivelyetched, so that a contact hole reaching the wiring 108 c is formed.Then, one electrode 110 of a display element is formed of a transparentconductive covering film. Through the above steps, a circuit of theelectro-optical display device is almost completed. FIG. 12E illustratesthe state up to this point.

FIGS. 14A and 14B each illustrate an example of circuit arrangement of apixel in the electro-optical display device obtained through the abovemanufacturing process. FIG. 14A corresponds to the stage illustrated inFIG. 12C and illustrates the state after the oxide semiconductor region106 is formed (or after the insulating film 107 is formed), which isseen from the above. The reference numerals in FIG. 14A correspond tothose in FIGS. 12A to 12E. Note that some elements such as theinsulating film 103 and the insulating film 107 are not illustrated inFIGS. 14A and 14B.

The wiring 104 a is a drain of the selection transistor and is also asignal line. The wiring 104 b serves as both a source of the selectiontransistor and gates of the N-channel driving transistor and theP-channel driving transistor. One end of the wiring 104 b has a largewidth and serves as one electrode of a capacitor here. A portion forconnection to an upper layer is provided in each of the wiring 104 a andthe island-shaped semiconductor regions 102 a and 102 b. In addition,the wiring 104 c serves as a high potential line. Note that the wiring104 c is not illustrated in FIGS. 12A to 12E.

FIG. 14B corresponds to the stage illustrated in FIG. 12D andillustrates the state after the wirings 108 a, 108 b, 108 c, and 108 dare formed, which is seen from the above. The reference numerals in FIG.14B correspond to those in FIGS. 12A to 12E.

The wiring 108 a serves as a gate of the selection transistor and alsoserves as a scan line in the row. The wiring 108 b is provided so as tocross the wiring 104 a, is in contact with the connection portionprovided in the wiring 104 c which serves as the high potential line,and is in contact with the connection portion provided in theisland-shaped semiconductor region 102 a (i.e., a drain of the N-channeldriving transistor), whereby the wiring 108 b functions as a connectionelectrode which connects the high potential line to the drain of theN-channel driving transistor.

The wiring 108 c is in contact with the connection portion provided inthe island-shaped semiconductor region 102 a (i.e., a source of theN-channel driving transistor) and the connection portion provided in theisland-shaped semiconductor region 102 b (i.e., a source of theP-channel driving transistor), whereby the wiring 108 c functions as aconnection electrode which connects the source of the N-channel drivingtransistor to the source of the P-channel driving transistor. Inaddition, in the wiring 108 c, a connection portion for connection tothe one electrode of the display element provided over the wiring 108 cis provided. In this embodiment, a plurality of connection portions(three connection portions in FIG. 14B) are provided by utilizing thelarge area of the wiring 108 c, so that the probability of connectionfailure is reduced.

The wiring 108 d serves as a scan line in the subsequent row. The wiring108 d is in contact with the connection portion provided in theisland-shaped semiconductor region 102 b (i.e., a drain of the P-channeldriving transistor), whereby the wiring 108 d functions as a connectionelectrode which connects the drain of the P-channel driving transistorto the scan line in the subsequent row. In addition, the wiring 108 dalso functions as the other electrode of the capacitor and a lowpotential line.

EMBODIMENT 9

In this embodiment, an example of a manufacturing method of theelectro-optical display devices described in Embodiments 1 to 7 will bedescribed. Although FIGS. 13A to 13E are cross-sectional viewsillustrating a manufacturing process of this embodiment, theyconceptually illustrate a manufacturing process and does not illustratea particular cross section. Note that as many of the methods, materials,and the like in this embodiment, the methods, materials, and the likedescribed in Embodiment 8 can be used. Therefore, the description isomitted except for the case of using particularly different material andconditions.

First, a substrate 201 is prepared. Then, over the substrate 201,island-shaped semiconductor regions 202 a and 202 b are formed of acrystalline semiconductor covering film such as a polycrystallinesilicon film or a single crystal silicon film. Furthermore, aninsulating film 203 is formed so as to cover the island-shapedsemiconductor regions 202 a and 202 b. FIG. 13A illustrates the state upto this point.

Next, wirings 204 a and 204 b are formed of a single-layer metal film ora multilayer metal film. Sidewalls may be formed on side surfaces of thewirings 204 a and 204 b as illustrated in FIG. 13B. The wiring 204 a isused as, for example, part of a scan line.

The wiring 204 a serves as a gate of a selection transistor using anoxide semiconductor which is formed later. Thus, it is preferable that amaterial used in an upper portion of the wiring 204 a have a workfunction higher than the electron affinity of the oxide semiconductor by0.5 eV or more. As examples of such a material, tungsten, gold,platinum, p-type silicon, and the like are given. Needless to say, amaterial having lower resistance may be provided in an lower layer inorder to increase conductivity.

Further, the wiring 204 b also serves as gates of the N-channel drivingtransistor and the P-channel driving transistor; thus, a material for alower part of the wiring 204 b, which has an appropriate physicalproperty value such as a work function, is preferable for determiningthe threshold voltage of the transistors. When these conditions are notsatisfied by one material, a multilayer film may be formed so that eachcondition is satisfied by each film. For example, a multilayer film of atitanium nitride film and a tungsten film may be used.

Although the example in which the same wiring is used as the gates ofthe N-channel driving transistor and the P-channel driving transistor isillustrated in FIG. 13B, the gates may be formed using differentmaterials in order to specifically control the threshold voltages.

After that, N-type regions 205 a are formed in the island-shapedsemiconductor region 202 a and P-type regions 205 b are formed in theisland-shaped semiconductor region 202 b by a known doping technique.After that, heat treatment at 250° C. to 450° C. is preferably performedin a hydrogen atmosphere. FIG. 13B illustrates the state up to thispoint.

Next, an insulating film 206 is formed by a known deposition method suchas a sputtering method. The insulating film 206 serves as a gateinsulating film of the selection transistor. It is preferable that thethickness of the insulating film 206 be greater than or equal to 10 nmand that the hydrogen concentration in the insulating film 206 be lowerthan 1×10¹⁸ cm⁻³, more preferably lower than 1×10¹⁶ cm⁻³. In order toobtain such a hydrogen concentration, heat treatment, chlorine plasmatreatment, or oxygen plasma treatment is preferably performed.

After that, an oxide semiconductor film is formed to a thickness of 3 nmto 30 nm by a sputtering method and is etched, so that an island-shapedoxide semiconductor region 207 is formed. Furthermore, over an entiresurface, an interlayer insulator 208 is formed of a material such assilicon oxide. The interlayer insulator 208 may be formed using not onlya single-layer film but also a multilayer film.

Further, the interlayer insulator 208 and the insulating film 206 whichoverlap with each other over the wirings 204 a and 204 b serve asdielectrics of a capacitor in many cases. On the other hand, theinterlayer insulator 208 and the insulating film 206 also serve asinterlayer insulators at an intersection portion of a signal line and ascan line; thus, a material and a thickness suitable for these purposesneed to be selected. In general, in the case where the interlayerinsulator 208 and the insulating film 206 are used as interlayerinsulators, they preferably have a large thickness and low dielectricconstant, while in the case where the interlayer insulator 208 and theinsulating film 206 are used as dielectrics of a capacitor, theypreferably have a small thickness and high dielectric constant. However,in this embodiment, the capacitance of the capacitor does notparticularly need to be increased; thus, even when the interlayerinsulator 208 has a thickness which is used for a normal interlayerinsulator, the interlayer insulator 208 can be used as a dielectric ofthe capacitor. FIG. 13C illustrates the state up to this point.

After that, wirings 209 a, 209 b, 209 c, 209 d, and 209 e are formed ofa conductive material. The wirings 209 a, 209 b, 209 c, 209 d, and 209 eeach serve as an electrode connected to a source or a drain of theselection transistor, the N-channel driving transistor, or the P-channeldriving transistor. In addition, the wiring 209 a serves as a signalline.

A material which forms an ohmic contact with an oxide semiconductor ispreferable as a material of the wirings 209 a, 209 b, 209 c, 209 d, and209 e. An example of such a material is a material whose work function Wis almost the same as or smaller than electron affinity φ (an energy gapbetween the lowest end of the conduction band of the oxide semiconductorand the vacuum level) of the oxide semiconductor. In other words,W<φ+0.3 [eV] is satisfied. As examples of the material, titanium,molybdenum, and titanium nitride are given. FIG. 13D illustrates thestate up to this point.

After that, an interlayer insulator 210 which has a flat surface isformed and is selectively etched, so that a contact hole reaching thewiring 209 d is formed. Then, one electrode 211 of a display element isformed of a transparent conductive covering film. Through the abovesteps, a circuit of the electro-optical display device is almostcompleted. FIG. 13E illustrates the state up to this point.

FIGS. 15A and 15B each illustrate an example of circuit arrangement of apixel in the electro-optical display device obtained through the abovemanufacturing process. FIG. 15A corresponds to the stage illustrated inFIG. 13C and illustrates the state after the oxide semiconductor region207 is formed (or after the interlayer insulator 208 is formed), whichis seen from the above. The reference numerals in FIG. 15A correspond tothose in FIGS. 13A to 13E. Note that the insulating film 203, theinsulating film 206, the interlayer insulator 208, and the like are notillustrated in FIGS. 15A and 15B.

The wiring 204 a serves as the gate of the selection transistor and alsoserves as a scan line in the row. The wiring 204 b serves as gates ofboth the N-channel driving transistor and the P-channel drivingtransistor. One end of the wiring 104 b has a large width and serves asone electrode of the capacitor. In addition, a wiring 204 c which servesas a high potential line and a wiring 204 d which serves as a scan linein the subsequent row are illustrated in FIG. 15A. Note that the wirings204 c and 204 d are not illustrated in FIGS. 13A to 13E.

Portions for connection to upper layers are provided in the oxidesemiconductor region 207, the wirings 204 a, 204 b, and 204 c, and theisland-shaped semiconductor regions 202 a and 202 b. Especially in theoxide semiconductor region 207, the area of each of the connectionportions is increased, whereby the probability of connection failure isreduced.

FIG. 15B corresponds to the stage illustrated in FIG. 13D andillustrates the state after the wirings 209 a, 209 b, 209 c, 209 d, and209 e are formed, which is seen from the above. The reference numeralsin FIG. 15B correspond to those in FIGS. 13A to 13E.

The wiring 209 a serves as a drain of the selection transistor and alsoserves as a signal line. The wiring 209 b is in contact with theconnection portion provided in the wiring 204 b, whereby the wiring 209b functions as a connection electrode which connects the source of theselection transistor to the wiring 204 b

The wiring 209 c is in contact with the connection portion provided inthe island-shaped semiconductor region 202 a (i.e., the drain of theN-channel driving transistor) and is in contact with the connectionportion provided in the wiring 204 c which serves as the high potentialline, whereby the wiring 209 c functions as a connection electrode whichconnects the drain of the N-channel driving transistor to the highpotential line. In addition, the wiring 209 c also functions as theother electrode of the capacitor.

The wiring 209 d is in contact with the connection portion provided inthe island-shaped semiconductor region 202 a (i.e., the source of theN-channel driving transistor) and the connection portion provided in theisland-shaped semiconductor region 202 b (i.e., the source of theP-channel driving transistor), whereby the wiring 209 d functions as aconnection electrode which connects the source of the N-channel drivingtransistor to the source of the P-channel driving transistor.

Further, in the wiring 209 d, a portion for connecting the one electrodeof the display element provided over the wiring 209 d is provided. Inthis embodiment, a plurality of connection portions (two connectionportions in FIG. 15B) are provided by utilization of the large area ofthe wiring 209 d. Moreover, the area of each of the connection portionsis increased, whereby the probability of connection failure is reduced.

The wiring 209 e is in contact with the connection portion provided inthe wiring 204 a which serves as the scan line in the row and theconnection portion provided in the island-shaped semiconductor region202 b (i.e., the drain of the P-channel driving transistor), whereby thewiring 209 e functions as a connection electrode which connects thewiring 204 a to the drain of the P-channel driving transistor. In thatcase, the wiring 204 a functions as a low potential line as well as thescan line.

The electro-optical display device having the wirings illustrated inFIGS. 15A and 15B corresponds to the circuit illustrated in FIG. 11A.

EMBODIMENT 10

In this embodiment, electronic devices using any of the electro-opticaldisplay devices described in Embodiments 1 to 9 will be described. Theseelectro-optical display devices can be used for devices such as personalcomputers, portable communication devices, image display devices, videoreproducing devices, imaging devices, game machines, and e-book readers.

This application is based on the Japanese Patent Application serial no.2010-109825 filed with the Japan Patent Office on May 12, 2010, theentire contents of which are hereby incorporated by reference.

1. An electro-optical display device comprising a pixel, the pixelcomprising: a first transistor; a second transistor; a third transistor;a capacitor; and a display element, wherein a source of the firsttransistor is connected to a gate of the second transistor, a gate ofthe third transistor, and one electrode of the capacitor, wherein asource of the second transistor and a source of the third transistor areconnected to one electrode of the display element, wherein a drain ofthe third transistor is connected to a low potential line, wherein thesecond transistor is an N-channel transistor and the third transistor isa P-channel transistor, wherein off-state current of the firsttransistor is less than or equal to 1/100 of leakage current of thedisplay element, and wherein capacitance of the capacitor is less thanor equal to 1/10 of capacitance of the display element.
 2. Theelectro-optical display device according to claim 1, wherein a drain ofthe second transistor is connected to a high potential line.
 3. Theelectro-optical display device according to claim 1, wherein a drain ofthe second transistor and the other electrode of the capacitor areconnected to a capacitor line.
 4. The electro-optical display deviceaccording to claim 1, wherein the first transistor is an N-channeltransistor.
 5. The electro-optical display device according to claim 1,wherein any one or two of the first transistor to the third transistorcomprises an oxide semiconductor.
 6. The electro-optical display deviceaccording to claim 5, wherein the oxide semiconductor comprises at leastone of indium, gallium, and zinc.
 7. The electro-optical display deviceaccording to claim 1, wherein at least one of the second transistor andthe third transistor comprises a polycrystalline semiconductor or asingle crystal semiconductor.
 8. The electro-optical display deviceaccording to claim 7, wherein the polycrystalline semiconductor isselected from polycrystalline silicon, polycrystalline silicongermanium, and polycrystalline germanium.
 9. The electro-optical displaydevice according to claim 7, wherein the single crystal semiconductor isselected from single crystal silicon, single crystal silicon germanium,and single crystal germanium.
 10. The electro-optical display deviceaccording to claim 1, wherein the electro-optical display devicecomprises a blue phase liquid crystal.
 11. The electro-optical displaydevice according to claim 1, wherein a frame period is longer than orequal to 100 seconds.
 12. The electro-optical display device accordingto claim 1, wherein time for writing of one screen in a frame is lessthan or equal to 0.2 milliseconds.
 13. An electro-optical display devicecomprising a pixel, the pixel comprising: a first transistor; a secondtransistor; a third transistor; a capacitor; and a display element,wherein a source of the first transistor is connected to a gate of thesecond transistor, a gate of the third transistor, and one electrode ofthe capacitor, wherein a source of the second transistor and a source ofthe third transistor are connected to one electrode of the displayelement, wherein a gate of the first transistor is connected to a firstscan line, wherein a drain of the third transistor is connected to asecond scan line, wherein the second transistor is an N-channeltransistor and the third transistor is a P-channel transistor, whereinoff-state current of the first transistor is less than or equal to 1/100of leakage current of the display element, and wherein capacitance ofthe capacitor is less than or equal to 1/10 of capacitance of thedisplay element.
 14. The electro-optical display device according toclaim 13, wherein a drain of the second transistor is connected to ahigh potential line.
 15. The electro-optical display device according toclaim 13, wherein a drain of the second transistor and the otherelectrode of the capacitor are connected to a capacitor line.
 16. Theelectro-optical display device according to claim 13, wherein the firsttransistor is an N-channel transistor.
 17. The electro-optical displaydevice according to claim 13, wherein any one or two of the firsttransistor to the third transistor comprises an oxide semiconductor. 18.The electro-optical display device according to claim 17, wherein theoxide semiconductor comprises at least one of indium, gallium, and zinc.19. The electro-optical display device according to claim 13, wherein atleast one of the second transistor and the third transistor comprises apolycrystalline semiconductor or a single crystal semiconductor.
 20. Theelectro-optical display device according to claim 19, wherein thepolycrystalline semiconductor is selected from polycrystalline silicon,polycrystalline silicon germanium, and polycrystalline germanium. 21.The electro-optical display device according to claim 19, wherein thesingle crystal semiconductor is selected from single crystal silicon,single crystal silicon germanium, and single crystal germanium.
 22. Theelectro-optical display device according to claim 13, wherein theelectro-optical display device comprises a blue phase liquid crystal.23. The electro-optical display device according to claim 13, wherein aframe period is longer than or equal to 100 seconds.
 24. Theelectro-optical display device according to claim 13, wherein time forwriting of one screen in a frame is less than or equal to 0.2milliseconds.
 25. An electro-optical display device comprising a pixel,the pixel comprising: a first transistor; a second transistor; a thirdtransistor; a capacitor; and a display element, wherein a source of thefirst transistor is connected to a gate of the second transistor, a gateof the third transistor, and one electrode of the capacitor, wherein asource of the second transistor and a source of the third transistor areconnected to one electrode of the display element, wherein a gate of thefirst transistor and a drain of the third transistor are connected to ascan line, wherein a drain of the second transistor and the otherelectrode of the capacitor are connected to a capacitor line, whereinthe second transistor is an N-channel transistor and the thirdtransistor is a P-channel transistor, wherein off-state current of thefirst transistor is less than or equal to 1/100 of leakage current ofthe display element, and wherein capacitance of the capacitor is lessthan or equal to 1/10 of capacitance of the display element.
 26. Theelectro-optical display device according to claim 25, wherein the firsttransistor is an N-channel transistor.
 27. The electro-optical displaydevice according to claim 25, wherein any one or two of the firsttransistor to the third transistor comprises an oxide semiconductor. 28.The electro-optical display device according to claim 27, wherein theoxide semiconductor comprises at least one of indium, gallium, and zinc.29. The electro-optical display device according to claim 25, wherein atleast one of the second transistor and the third transistor comprises apolycrystalline semiconductor or a single crystal semiconductor.
 30. Theelectro-optical display device according to claim 29, wherein the singlecrystal semiconductor is selected from single crystal silicon, singlecrystal silicon germanium, and single crystal germanium.
 31. Theelectro-optical display device according to claim 25, wherein theelectro-optical display device comprises a blue phase liquid crystal.32. The electro-optical display device according to claim 25, wherein aframe period is longer than or equal to 100 seconds.
 33. Theelectro-optical display device according to claim 25, wherein time forwriting of one screen in a frame is less than or equal to 0.2milliseconds.